\section{Sample And Hold}
\label{sec:SampleAndHold}

\subsection{Parameters and Performance Characteristics}

\subsubsection{Design}

The Sample and Hold circuit uses a Simple Transconductance Amplifier (Listing ~\ref{lst:STA}) with $G_m = 250nS$ and $R_{out}=1G\Ohm$. Several parameters were left as variables to be changed during various experiments. These parameters are described in Table~\ref{tbl:SAH_parameters}. Two circuits were designed, one with a pass-gate switch and another with a t-gate switch as shown in Figure \ref{fig:SAH_schematic}.

\begin{figure}[tbp]
\begin{center}
\begin{tabular}{c}
	\includegraphics[width=\columnwidth]{../Data/SampleAndHold_NFETswitch_schematic.png} \\
	(a) nFET Switch \\
	\includegraphics[width=\columnwidth]{../Data/SampleAndHold_TGATEswitch_schematic.png} \\
	(b) T-gate Switch \\	
\end{tabular}
\end{center}
\vspace*{-0.2cm}
\caption{Schematic for a Sample and Hold.}
\label{fig:SAH_schematic}
\end{figure}

\begin{table}[H] \centering
		\begin{tabular}{ccc}
			Parameter & Description & Default Value \\ \hline  
			$W$ & Width of the nFET &  $1.5\mu m$ \\   
			$V_{sw,high}$ & High value for V_{sw} &  $5V$ \\   
			$t_{r,f}$ & Rise and Fall time for V_{sw} &  $1ps$ \\  
			$C_s$ & Sampling Capacitance &  $100fF$ \\  
		\end{tabular}
		\caption{Parameters left as variables in the Sample and Hold circuit.}
		\label{tbl:SAH_parameters}
\end{table}

\subsubsection{Testing}

The variables in Table~\ref{tbl:SAH_parameters} for the circuit were changed for each simulation as shown in Figure~\ref{fig:SAH_Sims}.

\begin{figure*}[tbp]
\begin{center}
\begin{tabular}{cc}
	\includegraphics[width=3.5in]{../Data/SampleAndHold_NFETswitch_A.png} &
	\includegraphics[width=3.5in]{../Data/SampleAndHold_NFETswitch_B.png} \\
	(a) All Default & (b) $C_s = 500fF$ \\	
	\includegraphics[width=3.5in]{../Data/SampleAndHold_NFETswitch_C.png} &
	\includegraphics[width=3.5in]{../Data/SampleAndHold_NFETswitch_D.png} \\
	(c) $W=7.5\mu m$ & (d) $t_{r,f} = 10ns$ \\
	\includegraphics[width=3.5in]{../Data/SampleAndHold_NFETswitch_E.png} &
	\includegraphics[width=3.5in]{../Data/SampleAndHold_NFETswitch_F.png}  \\
	(e) $V_{sw,high} = 4V$ & (f) T-gate instead of nFET \\
\end{tabular}
\end{center}
\vspace*{-0.2cm}
\caption{Results for transient simulation of the Sample and Hold circuit with changing parameters.}
\label{fig:SAH_Sims}
\end{figure*}

\subsubsection{Evaluation} 

Three different characteristics are used to evaluate the sample and hold circuit:

\begin{enumerate}
	\item $Error_{feedthrough}$ - measured as the difference in output voltage just after the sample period (switch on) ended. It can be approximated as $Error_{clock} + Error_{charge} $
		\begin{itemize}
			\item $Error_{clock}$ $\frac{C_{ov} \Delta V_{sw}}{C_{total}}$ - The error caused due to $V_{sw}$ coupling into $V_s$ through $C_{ov}$. Primarily dependent upon the $V_{sw}$ and $C_s$.
			\item $Error_{charge}$ $\frac{C_{ox} (V_{gs} - V_{th})}{2 C_{total}}$ - The error caused due to $V_{sw}$ coupling into $V_s$ through $C_{ox}$. Primarily dependent upon the sampled voltage, $V_{in}$.
		\end{itemize}
	\item $Error_{leakage}$ - Charge in the capacitor lost through parasitics. Measured as a loss in voltage over time after the perturbation from feedthrough has ended.
	\item $t_{settle}$ - Time taken to acquire a sample. In this case, measured as the time it takes for $V_{out}$ to get from $2.25V$ to $99-99.9\%$ of $2.75V$.
\end{enumerate}

\begin{table*}[tbp] \centering
		\begin{tabular}{c|ccc}
			Simulation & $Error_{feedthrough}$ & $Error_{leakage}$ & $t_{settle}$ \\ \hline 
			(a) All Default & $42.61mV$ & $400mV/s$ & $7.0186ns (99.9\%)$ \\
			(b) $C_s = 500fF$  & $8.65mV$ & $15.5mV/s$ & $36.116ns (99.9\%)$ \\
			(c) $W=7.5\mu m$ & $204.03mV$ & $1.84V/s$ & $1.361ns (99.9\%)$ \\
			(d) $t_{r,f} = 10ns$ & $34.239mV$ & $324.113mV/s$ & $11.051ns (99.9\%)$ \\
			(e) $V_{sw,high} = 4V$ & $9.13mV$ & $104.980mV/s$ & $160ns (99\%)$ \\
			(f) T-gate instead of nFET & $22.81mV$ & $385.191mV/s$ & $15.375ns (99.9\%)$ \\
		\end{tabular}
		\caption{Results for the evaluation of the Sample and Hold circuit with varying parameters.}
		\label{tbl:SAH_charac_results}
\end{table*}

The results from Figure \ref{fig:SAH_Sims} and Table \ref{tbl:SAH_charac_results} are analyzed below:

\begin{itemize}
	\item (a) All Default - The control experiment, with all values at default and the circuit working as expected.
	\item (b) $C_s = 500fF$ - As expected, the $Error_{feedthrough}$ reduces significantly. However, $t_{settle}$ increases due to the extra capacitance.
	\item (c) $W=7.5\mu m$ - $Error_{feedthrough}$ increases significantly due to $Error_{charge}$. Also note that $t_{settle}$ decreases because more current can get through the switch.
	\item (d) $t_{r,f} = 10ns$ - $Error_{feedthrough}$ reduces since the switch is turning off slower, allowing the circuit to settle.
	\item (e) $V_{sw,high} = 4V$ - $Error_{feedthrough}$ goes down significantly because of the reduction of the gate voltage for the switch. A big loss is that the output voltage is extremely slow to get to the input voltage. So much so that the $t_{settle}$ measurement is made at the $90\%$ mark.
	\item (f) T-gate instead of nFET - Using a transmission gate cuts the $Error_{feedthrough}$ in half but doubles the $t_{settle}$.
\end{itemize}

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\subsection{Feedthrough Dependance on Sampled Voltage}

\subsubsection{Design}

In order to characterize the dependance of feedthrough on sampled voltage, $V_{in}$ is replaced with a piecewise-linear voltage source starting at $0V$ and ramping up to $5V$. Two circuits were designed, one with a pass-gate switch and another with a t-gate switch as shown in Figure \ref{fig:SAHS_schematic}.

\begin{figure}[H]
\begin{center}
\begin{tabular}{c}
	\includegraphics[width=3.5in]{../Data/SampleAndHold_NFETswitch_Sample_schematic.png} \\
	\includegraphics[height=1.2in]{../Data/SampleAndHold_TGATEswitch_Sample_schematic.png} \\
\end{tabular}
\end{center}
\vspace*{-0.2cm}
\caption{Schematic for a Sample and Hold with $V_{in}$ as a piecewise-linear voltage source. (a) nFET (b) Tgate}
\label{fig:SAHS_schematic}
\end{figure}

\subsubsection{Testing}

Transient simulations were performed to observe the circuit's behavior as the input voltage ramped to $5V$.

\begin{figure}[H]
\begin{center}
\begin{tabular}{c}
	\includegraphics[width=3.5in]{../Data/SampleAndHold_NFETswitch_Sample_results.png} \\
	\includegraphics[width=3.5in]{../Data/SampleAndHold_TGATEswitch_Sample_results.png} \\
\end{tabular}
\end{center}
\vspace*{-0.2cm}
\caption{Transient simulation results for Sample and Hold with $V_{in}$ as a piecewise-linear voltage source. Also shown is the error between input and output as a function of input voltage. (a) nFET Switch (b) T-gate Switch }
\label{fig:SAHS_results}
\end{figure}

\subsubsection{Evaluation}

In order to characterize the circuits, the error between the input and output voltages was calculated. This was done using plot( sample(VT("/Vin") - lshift(VT("/Vout"),-1u),1u,10m,"linear",50u ))

When using an nFET switch, the error between starts high but decreases as the input voltage increases. This is because $Error_{charge}$ decreases as $V_{gs}$ decreases with $V_s$ being the input voltage. However, at approximately $V_{in} = 4V$ the error starts increasing significantly because th nFET stops conducting as $V_{gs}$ becomes less than $V_{th}$.

When using the tgate-switch, the error is symmetrical with a zero at midrail. There is still a dependance on the sampled voltage but the error remains low with no transistors getting of operation.